Difference between revisions of "VPP/AArch64"

Revision as of 13:41, 8 November 2017

Meeting Details

Weekly on Wednesdays, 8-9am PT. FD.io Zoom Meeting room

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    Meeting ID: 530 118 5804
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IRC Channel

#fdio-arm on freenode.net

Recent Patches

Might want to have a look at this patch which adds "make config"

https://gerrit.fd.io/r/#/c/9200/

Known Issues

Compilation may fail on systems with less than 1GB memory per core. One workaround is to search for -j in build-root/Makefile and multiply by 1 instead of 2.

GCC 5.3.x ICEs during FP register allocation. Please use GCC 5.4+.

Unit tests

Timing consideration on platform: hierofalcon with cortex A57 & fedora26

Issues

1. Random initialization failures; current workaround is to disable ASLR: sysctl -w kernel.randomize_va_space=0

2. Some tests need timeout finetuning:

Example test_cflow_packet:

assertAlmostEqual(cflow[IPFIX].exportTime, nowUTC, delta=5)

Test order

Some tests are not meant to be played alone.

For example the test_l2bd_arp_term_\d+ list

• test_1: create 5 hosts
• test_2: delete 3 of the hosts created by test_1

...

Those tests should be played grouped. For example in the case above ;

# works
make test TEST=*.TestL2bdArpTerm.*
# does not work
make test V=1 TEST=*.TestL2bdArpTerm.test_l2bd_arp_term_01
make test V=1 TEST=*.TestL2bdArpTerm.test_l2bd_arp_term_02
...

Packaging

CSIT func & perf

TODO

AArch64 Porting & Tuning

Support multiple cache line sizes per architecture. AArch64 is currently hard coded to 128B. For native build, inspect ARMv8 Main ID Register in Makefile and pass cache line size as compiler option, e.g. -DCACHE_LINE_SIZE=128.

Investigate "show cpu" output and Arm CPU feature detection (AES, SHA1, SHA2, CRC32, ATOMICS) via hwcaps. src/vppinfra/cpu.[ch]

Review use of Arm architected timer in src/vppinfra/time.[ch]

Use ISB or YIELD in src/vppinfra/smp.h

Use REV in src/vppinfra/byte_order.h

Review use of __sync_xxx/__atomic_xxx builtins to ensure correct memory ordering on non-TSO machines.

Investigate hash performance (CRC32 vs xxhash) e.g. in src/vppinfra/bihash_8_8.h. Dependent on Arm CPU feature detection.

Investigate memcpy performance (src/vppinfra/string.h); both inlined-by-compiler and libc versions.

Investigate dual/quad loop tuning, e.g. l2_forward().

SIMD

• CLIB_HAVE_VEC128 also covers 256-bit. Add CLIB_HAVE_VEC256?
• ixge.[ch] - 128-bit vector types with plain C. Needs to be enabled.
• mheap.c - requires NEON implementation of is_equal
• hash.h - requires NEON implementation of irotate
• vnet_classify.h - 128-bit vector types with plain C. Needs to be enabled.
• vhost-user.c - SSE4.2 only. Implement range search using NEON.
• ip4_mtrie.h - 128-bit vector types with plain C. Needs to be enabled.

Meeting Minutes

10/25/2017

• Gabriel working on vpp init failure in linux_pci_init()
• Kumar to check with GeorgeZ on Huawei boards shipped to CSIT; need to verify tests also on this environment (package versions from distro)
• Brian to check whether anything else needs to be done besides 'make test' for upstream enablement