VPP/AArch64

Patches

lb plugin - fix format() type mismatches	Merged 10/16	https://gerrit.fd.io/r/#/c/8755/
Use AESNI=y only on x86_64 machines	Merged 10/14	https://gerrit.fd.io/r/#/c/8622/
Improved arm64 chip detection	Merged 9/11	https://gerrit.fd.io/r/#/c/8372/
Native arm64 build: dpdk/Makefile change	Merged 8/31	https://gerrit.fd.io/r/#/c/8228/

Known Issues

GCC 5.3.x ICEs during FP register allocation. Please use GCC 5.4+.

CSIT unit tests

make test-debug status: ?

Failed:

• TestIP6VrfMultiInst.test_ip6_vrf_02
• TestL2bdArpTerm.test_l2bd_arp_term_10
• TestL2bdArpTerm.test_l2bd_arp_term_14
• TestL2bdArpTerm.test_l2bd_arp_term_02
• TestL2bdArpTerm.test_l2bd_arp_term_11
• TestL2bdArpTerm.test_l2bd_arp_term_04
• TestL2bdArpTerm.test_l2bd_arp_term_13
• TestIP6VrfMultiInst.test_ip6_vrf_02
• TestIPv4FibCrud.test_3_add_new_routes
• TestIp4VrfMultiInst.test_ip4_vrf_02
• TestL2bdMultiInst.test_l2bd_inst_02
• TestL2bdMultiInst.test_l2bd_inst_03
• TestIPv4FibCrud.test_2_del_routes

make test-all-debug status: ?

make test

status: no additional test failure

VPP cleanup failure:

• TestIPPunt.test_ip_punt
• TestIPv4FibCrud.test_2_del_routes
• TestIPv4FibCrud.test_3_add_new_routes
• TestIp4VrfMultiInst.test_ip4_vrf_02
• TestIP6VrfMultiInst.test_ip6_vrf_02
• TestL2bdMultiInst.test_l2bd_inst_03

Other failures:

• TestL2bdArpTerm.test_l2bd_arp_term_10
• TestL2bdArpTerm.test_l2bd_arp_term_11
• TestL2bdArpTerm.test_l2bd_arp_term_13
• TestL2bdArpTerm.test_l2bd_arp_term_02
• TestL2bdArpTerm.test_l2bd_arp_term_14
• TestL2bdArpTerm.test_l2bd_arp_term_04

Unknown (vpp init error):

• TestIpIrb.test_0103_ip6_irb_1
• TestIpIrb.test_1201_ip6_irb_1
• TestIpIrb.test_1112_ip6_irb_1
• TestL2fib.test_l2_fib_delete12
• TestSRv6.test_SRv6_End_X_with_PSP
• TestL2bdMultiInst.test_l2bd_inst_02

make test-all

status: no additional test failure

Misc

Support multiple cache line sizes per architecture. AArch64 is currently hard coded to 128B. For native build, inspect ARMv8 Main ID Register in Makefile and pass cache line size as compiler option, e.g. -DCACHE_LINE_SIZE=128.

Investigate "show cpu" output and Arm CPU feature detection (AES, SHA1, SHA2, CRC32, ATOMICS) via hwcaps. src/vppinfra/cpu.[ch]

Review use of Arm architected timer in src/vppinfra/time.[ch]

Use ISB or YIELD in src/vppinfra/smp.h

Use REV in src/vppinfra/byte_order.h

Review use of __sync_xxx/__atomic_xxx builtins to ensure correct memory ordering on non-TSO machines.

Investigate hash performance (CRC32 vs xxhash) e.g. in src/vppinfra/bihash_8_8.h. Dependent on Arm CPU feature detection.

Investigate memcpy performance (src/vppinfra/string.h); both inlined-by-compiler and libc versions.

SIMD

• Investigate uses of CLIB_HAVE_VEC128 that are not implemented on Arm (mheap_bootstrap.h, vhost-user.c, ixge.c)
• Investigate uses of splat for initialization
• Investigate uses of SIMD types with plain C bit-wise/arith ops (code generation) (dpdk/node.c, ...)

Investigate current tuning of dual/quad loop optimizations for hiding memory latency, e.g. l2_forward().